MEGA128CAN Datasheet, PDF (189/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
USART Register
Description
USART0 I/O Data Register –
UDR0
USART1 I/O Data Register –
UDR1
USART0 Control and Status
Register A – UCSR0A
USART1 Control and Status
Register A – UCSR1A
Bit
7
Read/Write
R/W
Initial Value
0
6
R/W
0
5
R/W
0
4
3
RXB0[7:0]
TXB0[7:0]
R/W
R/W
0
0
2
R/W
0
1
R/W
0
0
UDR0 (Read)
UDR0 (Write)
R/W
0
Bit
7
Read/Write
R/W
Initial Value
0
6
R/W
0
5
R/W
0
4
3
RXB1[7:0]
TXB1[7:0]
R/W
R/W
0
0
2
R/W
0
1
R/W
0
0
UDR1 (Read)
UDR1 (Write)
R/W
0
• Bit 7:0 – RxBn7:0: Receive Data Buffer (read access)
• Bit 7:0 – TxBn7:0: Transmit Data Buffer (write access)
The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Regis-
ters share the same I/O address referred to as USARTn Data Register or UDRn. The
Transmit Data Buffer Register (TXBn) will be the destination for data written to the
UDRn Register location. Reading the UDRn Register location will return the contents of
the Receive Data Buffer Register (RXBn).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter
and set to zero by the Receiver.
The transmit buffer can only be written when the UDREn flag in the UCSRnA Register is
set. Data written to UDRn when the UDREn flag is not set, will be ignored by the
USARTn Transmitter. When data is written to the transmit buffer, and the Transmitter is
enabled, the Transmitter will load the data into the Transmit Shift Register when the
Shift Register is empty. Then the data will be serially transmitted on the TxDn pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever
the receive buffer is accessed.
Bit
Read/Write
Initial Value
7
RXC0
R
0
6
TXC0
R/W
0
5
UDRE0
R
1
4
FE0
R
0
3
DOR0
R
0
2
UPE0
R
0
1
U2X0
R/W
0
0
MPCM0
R/W
0
UCSR0A
Bit
Read/Write
Initial Value
7
RXC1
R
0
6
TXC1
R/W
0
5
UDRE1
R
1
4
FE1
R
0
3
DOR1
R
0
2
UPE1
R
0
1
U2X1
R/W
0
0
MPCM1
R/W
0
UCSR1A
• Bit 7 – RXCn: USARTn Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the
receive buffer is empty (i.e., does not contain any unread data). If the Receiver is dis-
abled, the receive buffer will be flushed and consequently the RXCn bit will become
zero. The RXCn flag can be used to generate a Receive Complete interrupt (see
description of the RXCIEn bit).
4250E–CAN–12/04
189