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| MEGA128CAN Datasheet, PDF (399/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER | |||
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AT90CAN128
Mnemonics
BRIE
BRID
SBI
CBI
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
MOV
MOVW
LDI
LD
LD
LD
LD
LD
LD
LDD
LD
LD
LD
LDD
LDS
ST
ST
ST
ST
ST
ST
STD
ST
ST
ST
STD
STS
LPM
LPM
LPM
ELPM
ELPM
ELPM
SPM
Operands
Description
k
Branch if Interrupt Enabled
k
Branch if Interrupt Disabled
BIT AND BIT-TEST INSTRUCTIONS
P,b
Set Bit in I/O Register
P,b
Clear Bit in I/O Register
Rd
Logical Shift Left
Rd
Logical Shift Right
Rd
Rotate Left Through Carry
Rd
Rotate Right Through Carry
Rd
Arithmetic Shift Right
Rd
Swap Nibbles
s
Flag Set
s
Flag Clear
Rr, b
Bit Store from Register to T
Rd, b
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
DATA TRANSFER INSTRUCTIONS
Rd, Rr
Move Between Registers
Rd, Rr
Copy Register Word
Rd, K
Load Immediate
Rd, X
Load Indirect
Rd, X+
Load Indirect and Post-Inc.
Rd, - X
Load Indirect and Pre-Dec.
Rd, Y
Load Indirect
Rd, Y+
Load Indirect and Post-Inc.
Rd, - Y
Load Indirect and Pre-Dec.
Rd,Y+q
Load Indirect with Displacement
Rd, Z
Load Indirect
Rd, Z+
Load Indirect and Post-Inc.
Rd, -Z
Load Indirect and Pre-Dec.
Rd, Z+q
Load Indirect with Displacement
Rd, k
Load Direct from SRAM
X, Rr
Store Indirect
X+, Rr
Store Indirect and Post-Inc.
- X, Rr
Store Indirect and Pre-Dec.
Y, Rr
Store Indirect
Y+, Rr
Store Indirect and Post-Inc.
- Y, Rr
Store Indirect and Pre-Dec.
Y+q,Rr
Store Indirect with Displacement
Z, Rr
Store Indirect
Z+, Rr
Store Indirect and Post-Inc.
-Z, Rr
Store Indirect and Pre-Dec.
Z+q,Rr
Store Indirect with Displacement
k, Rr
Store Direct to SRAM
Load Program Memory
Rd, Z
Load Program Memory
Rd, Z+
Load Program Memory and Post-Inc
Extended Load Program Memory
Rd, Z
Extended Load Program Memory
Rd, Z+
Extended Load Program Memory and Post-Inc
Store Program Memory
4250EâCANâ12/04
Operation
if ( I = 1) then PC â PC + k + 1
if ( I = 0) then PC â PC + k + 1
I/O(P,b) â 1
I/O(P,b) â 0
Rd(n+1) â Rd(n), Rd(0) â 0
Rd(n) â Rd(n+1), Rd(7) â 0
Rd(0)âC,Rd(n+1)â Rd(n),CâRd(7)
Rd(7)âC,Rd(n)â Rd(n+1),CâRd(0)
Rd(n) â Rd(n+1), n=0..6
Rd(3..0)âRd(7..4),Rd(7..4)âRd(3..0)
SREG(s) â 1
SREG(s) â 0
T â Rr(b)
Rd(b) â T
Câ1
Câ0
Nâ1
Nâ0
Zâ1
Zâ0
Iâ1
Iâ0
Sâ1
Sâ0
Vâ1
Vâ0
Tâ1
Tâ0
Hâ1
Hâ0
Rd â Rr
Rd+1:Rd â Rr+1:Rr
Rd â K
Rd â (X)
Rd â (X), X â X + 1
X â X - 1, Rd â (X)
Rd â (Y)
Rd â (Y), Y â Y + 1
Y â Y - 1, Rd â (Y)
Rd â (Y + q)
Rd â (Z)
Rd â (Z), Z â Z+1
Z â Z - 1, Rd â (Z)
Rd â (Z + q)
Rd â (k)
(X) â Rr
(X) â Rr, X â X + 1
X â X - 1, (X) â Rr
(Y) â Rr
(Y) â Rr, Y â Y + 1
Y â Y - 1, (Y) â Rr
(Y + q) â Rr
(Z) â Rr
(Z) â Rr, Z â Z + 1
Z â Z - 1, (Z) â Rr
(Z + q) â Rr
(k) â Rr
R0 â (Z)
Rd â (Z)
Rd â (Z), Z â Z+1
R0 â (RAMPZ:Z)
Rd â (RAMPZ:Z)
Rd â (RAMPZ:Z), RAMPZ:Z â RAMPZ:Z+1
(Z) â R1:R0
Flags
None
None
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
#Clocks
1/2
1/2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
-
399
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