MEGA128CAN Datasheet, PDF (270/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

Figure 132. ADC Timing Diagram, Auto Triggered Conversion
One Conversion
Next Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
1
2
3
4
5
6
7
8
9
10 11 12 13
1
2
MUX and REFS
Update
Sample &
Hold
Conversion
Complete
Sign and MSB of Result
LSB of Result
Prescaler
Reset
Figure 133. ADC Timing Diagram, Free Running Conversion
One Conversion
Next Conversion
Cycle Number ^{11 12 13 1}
2
3
4
ADC Clock
ADSC
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Conversion
Complete
Sample & Hold
MUX and REFS
Update
Table 99. ADC Conversion Time
Condition
First
Conversion
Sample & Hold
14.5
(Cycles from Start of Convertion)
Conversion Time
(Cycles)
25
Normal
Conversion,
Single Ended
1.5
Auto Triggered
Convertion
2
13
13.5
Differential Channels
When using differential channels, certain aspects of the conversion need to be taken
into consideration.
Differential conversions are synchronized to the internal clock CK_ADC2 equal to half the
ADC clock frequency. This synchronization is done automatically by the ADC interface
in such a way that the sample-and-hold occurs at a specific phase of CK_ADC2. A conver-
sion initiated by the user (i.e., all single conversions, and the first free running
conversion) when CK_ADC2 is low will take the same amount of time as a single ended
conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion ini-
tiated by the user when CK_ADC2 is high will take 14 ADC clock cycles due to the
synchronization mechanism. In Free Running mode, a new conversion is initiated imme-
270 AT90CAN128
4250E–CAN–12/04