MEGA128CAN Datasheet, PDF (193/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data
bits (Character SiZe) in a frame the Receiver and Transmitter use.
Table 82. UCSZn Bits Settings
UCSZn2
UCSZn1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
UCSZn0
0
1
0
1
0
1
0
1
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous
mode is used. The UCPOLn bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCKn).
Table 83. UCPOLn Bit Settings
Transmitted Data Changed
UCPOLn (Output of TxDn Pin)
0
Rising XCK Edge
1
Falling XCK Edge
Received Data Sampled
(Input on RxDn Pin)
Falling XCK Edge
Rising XCK Edge
USART0 Baud Rate Registers
– UBRR0L and UBRR0H
Bit
Read/Write
Initial Value
15
14
13
12
11
10
9
8
–
–
–
–
UBRR0[11:8]
UBRR0H
UBRR0[7:0]
UBRR0L
7
6
5
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
USART1 Baud Rate Registers
– UBRR1L and UBRR1H
Bit
Read/Write
Initial Value
15
14
13
12
11
10
9
8
–
–
–
–
UBRR1[11:8]
UBRR1H
UBRR1[7:0]
UBRR1L
7
6
5
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4250E–CAN–12/04
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