MEGA128CAN Datasheet, PDF (246/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

General CAN Registers
CAN General Control Register
- CANGCON
Bit
Read/Write
Initial Value
7
ABRQ
R/W
0
6
OVRQ
R/W
0
5
4
3
2
1
0
TTC SYNTTC LISTEN TEST ENA/STB SWRES CANGCON
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
• Bit 7 – ABRQ: Abort Request
This is not an auto resettable bit.
– 0 - no request.
– 1 - abort request: a reset of CANEN1 and CANEN2 registers is done. The
pending communications are immediately disabled and the on-going one will be
normally terminated, setting the appropriate status flags.
Note that CONCDMOB register remain unchanged.
• Bit 6 – OVRQ: Overload Frame Request
This is not an auto resettable bit.
– 0 - no request.
– 1 - overload frame request: send an overload frame after the next received
frame.
The overload frame can be traced observing OVFG in CANGSTA register (c.f. Figure
119 on page 237).
• Bit 5 – TTC: Time Trigger Communication
– 0 - no TTC.
– 1- TTC mode.
• Bit 4 – SYNTTC: Synchronization of TTC
This bit is only used in TTC mode.
– 0 - the TTC timer is caught on SOF.
– 1 - the TTC timer is caught on the last bit of the EOF.
• Bit 3 – LISTEN: Listening Mode
– 0 - no listening mode.
– 1 - listening mode.
• Bit 2 – TEST: Test Mode
– 0 - no test mode
– 1 - test mode: intend for factory testing and not for customer use.
Note: CAN may malfunction if this bit is set.
• Bit 1 – ENA/STB: Enable / Standby Mode
Because this bit is a command and is not immediately effective, the ENFG bit in CANG-
STA register gives the true state of the chosen mode.
– 0 - standby mode: the on-going communication is normally terminated and the
CAN channel is frozen (the CONMOB bits of every MOb do not change). The
transmitter constantly provides a recessive level. In this mode, the receiver is
not enabled but all the registers and mailbox remain accessible from CPU.
– 1 - enable mode: the CAN channel enters in enable mode once 11 recessive
bits has been read.
246 AT90CAN128
4250E–CAN–12/04