MEGA128CAN Datasheet, PDF (243/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
Interrupts
Interrupt organization
The different interrupts are:
• Interrupt on receive completed OK,
• Interrupt on transmit completed OK,
• Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error),
• Interrupt on frame buffer full,
• Interrupt on “Bus Off” setting,
• Interrupt on overrun of CAN timer.
The general interrupt enable is provided by ENIT bit and the specific interrupt enable for
CAN timer overrun is provided by ENORVT bit.
Figure 124. CAN Controller Interrupt Structure
CANSTMOB.6 TXOK[i]
CANSTMOB.5 RXOK[i]
CANSTMOB.4 BERR[i]
CANSTMOB.3 SERR[i]
CANSTMOB.2 CERR[i]
CANSTMOB.1 FERR[i]
CANSTMOB.0 AERR[i]
CANGIE.4
ENTX
CANGIE.5
ENRX
CANGIE.3
ENERR
CANGIE.2
ENBX
CANSIT 1/2
SIT[i]
CANIE 1/2
IEMOB[i]
i=0
i=14
CANGIE.1
ENERG
CANGIE.6
ENBOFF
CANGIT.7
CANIT
CANGIE.7
ENIT
CANGIT.4
BXOK
CAN IT
CANGIT.3
CANGIT.2
CANGIT.1
CANGIT.0
SERG
CERG
FERG
AERG
CANGIT.6
BOFFI
CANGIE.0
ENOVRT
CANGIT.5 OVRTIM
OVR IT
4250E–CAN–12/04
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