MEGA128CAN Datasheet, PDF (371/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
Parallel Programming Characteristics
Figure 177. Parallel Programming Timing, Including some General Timing
Requirements
XTAL1
Data & Contol
(DATA, XA0/1, BS1, BS2)
PAGEL
WR
RDY/BSY
t_DVXH
t_XHXL
t_XLWL
t_XLDX
t_BVPH
t_PHPL
t_PLBX t _BVWL
t_PLWL
t_WLWH
WLRL
t_WLBX
t_WLRH
XTAL1
Figure 178. Parallel Programming Timing, Loading Sequence with Timing
Requirements⁽¹⁾
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
t _XLXH
LOAD DATA LOAD DATA
(HIGH BYTE)
t_XLPH
t_PLXH
LOAD ADDRESS
(LOW BYTE)
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 177 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply
to loading operation.
4250E–CAN–12/04
371