MEGA128CAN Datasheet, PDF (304/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3
when the power supply is 5.0V and AREF is externally connected to V_CC.
The lower limit is:
The upper limit is:
1024 ⋅ 1,5V ⋅ 0,95 ⁄ 5V = 291 = 0x123
1024 ⋅ 1,5V ⋅ 1,05 ⁄ 5V = 323 = 0x143
The recommended values from Table 111 are used unless other values are given in the
algorithm in Table 112. Only the DAC and port pin values of the Scan Chain are shown.
The column “Actions” describes what JTAG instruction to be used before filling the
Boundary-scan Register with the succeeding columns. The verification should be done
on the data scanned out when scanning in the data on the same row in the table.
Table 112. Algorithm for Using the ADC
Step
1
2
3
4
5
6
7
8
9
10
11
Actions
SAMPLE_
PRELOAD
EXTEST
Verify the
COMP bit
scanned
out to be 0
Verify the
COMP bit
scanned
out to be 1
ADCEN
1
1
1
1
1
1
1
1
1
1
1
DAC
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
HOLD
1
0
1
1
1
1
0
1
1
1
1
PRECH
1
1
1
1
0
1
1
1
1
0
1
PA3.
Data
0
0
0
0
0
0
0
0
0
0
0
PA3.
Control
0
0
0
0
0
0
0
0
0
0
0
PA3.
Pullup_
Enable
0
0
0
0
0
0
0
0
0
0
0
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock
frequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency
has to be at least five times the number of scan bits divided by the maximum hold time,
t_hold,max
304 AT90CAN128
4250E–CAN–12/04