MEGA128CAN Datasheet, PDF (361/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
SPI Timing Characteristics
See Figure 171 and Figure 172 for details.
Table 139. SPI Timing Parameters
Description
Mode
1
SCK period
Master
2
SCK high/low
Master
3
Rise/Fall time
Master
4
Setup
Master
5
Hold
Master
6
Out to SCK
Master
7
SCK to out
Master
8
SCK to out high
Master
9
SS low to out
Slave
10
SCK period
11
SCK high/low ⁽¹⁾
Slave
Slave
12
Rise/Fall time
Slave
13
Setup
Slave
14
Hold
Slave
15
SCK to out
Slave
16
SCK to SS high
Slave
17
SS high to tri-state
Slave
18
SS low to SCK
Slave
Min.
4 • t_ck
2 • t_ck
10
t_ck
20
2 • t_ck
Typ.
See Table 74
50% duty cycle
3.6
10
10
0.5 • t_sck
10
10
15
15
10
Notes: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t_CLCL for f_CK < 12 MHz
- 3 t_CLCL for f_CK >12 MHz
Figure 171. SPI Interface Timing Requirements (Master Mode)
Max.
ns
1.6 µs
ns
SS
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MISO
(Data Input)
MOSI
(Data Output)
6
45
MSB
7
MSB
...
...
1
2
2
LSB
LSB
3
8
4250E–CAN–12/04
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