MEGA128CAN Datasheet, PDF (372/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

Figure 179. Parallel Programming Timing, Reading Sequence (within the Same Page)
with Timing Requirements⁽¹⁾
XTAL1
BS1
OE
DATA
LOAD ADDRESS
(LOW BYTE)
t_XLOL
t_OLDV
ADDR0 (Low Byte)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
t_BVDV
LOAD ADDRESS
(LOW BYTE)
DATA (Low Byte)
t_OHDZ
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 177 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply
to reading operation.
Table 150. Parallel Programming Characteristics, V_CC = 5V ± 10%
Symbol Parameter
Min. Typ.
V_PP
Programming Enable Voltage
11.5
I_PP
Programming Enable Current
t_DVXH
Data and Control Valid before XTAL1 High
67
t_XLXH
XTAL1 Low to XTAL1 High
200
t_XHXL
XTAL1 Pulse Width High
150
t_XLDX
Data and Control Hold after XTAL1 Low
67
t_XLWL
XTAL1 Low to WR Low
0
t_XLPH
XTAL1 Low to PAGEL high
0
t_PLXH
PAGEL low to XTAL1 high
150
t_BVPH
BS1 Valid before PAGEL High
67
t_PHPL
PAGEL Pulse Width High
150
t_PLBX
BS1 Hold after PAGEL Low
67
t_WLBX
BS2/1 Hold after WR Low
67
t_PLWL
PAGEL Low to WR Low
67
t_BVWL
BS1 Valid to WR Low
67
t_WLWH
WR Pulse Width Low
150
t_WLRL
WR Low to RDY/BSY Low
0
t_WLRH
WR Low to RDY/BSY High⁽¹⁾
3.7
t_{WLRH_CE} WR Low to RDY/BSY High for Chip Erase⁽²⁾
7.5
t_XLOL
XTAL1 Low to OE Low
0
Max.
12.5
250
1
5
10
Units
V
µA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
ns
372 AT90CAN128
4250E–CAN–12/04