MEGA128CAN Datasheet, PDF (370/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

Figure 175. External Memory Timing (SRWn1 = 1, SRWn0 = 0)
T1
System Clock (CLK_CPU)
ALE
A15:8 Prev. addr.
DA7:0 Prev. data
WR
DA7:0 (XMBK = 0)
RD
T2
T3
1
4
7
2 3a 13
Address XX
6
3b
Address
5
10
8
T4
T5
T6
Address
15
Data
16
9
Data
12
14
11
T1
System Clock (CLK_CPU)
ALE
A15:8 Prev. addr.
DA7:0 Prev. data
WR
DA7:0 (XMBK = 0)
RD
Figure 176. External Memory Timing (SRWn1 = 1, SRWn0 = 1)⁽¹⁾
T2
T3
T4
T5
T6
T7
1
4
7
2 3a 13
Address
15
Address XX
Data
6
16
14
3b
9
11
Address
5
10
Data
8
12
Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction
accesses the RAM (internal or external).
370 AT90CAN128
4250E–CAN–12/04