MEGA128CAN Datasheet, PDF (279/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
ADC Register Description
ADC Multiplexer Selection
Register – ADMUX
Bit
Read/Write
Initial Value
7
REFS1
R/W
0
6
REFS0
R/W
0
5
ADLAR
R/W
0
4
MUX4
R/W
0
3
MUX3
R/W
0
2
MUX2
R/W
0
1
MUX1
R/W
0
0
MUX0
R/W
0
ADMUX
• Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 101. If these bits
are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set). The internal voltage reference options may not be
used if an external reference voltage is being applied to the AREF pin.
Table 101. Voltage Reference Selections for ADC
REFS1 REFS0 Voltage Reference Selection
0
0
AREF, Internal Vref turned off
0
1
AV_CC with external capacitor on AREF pin
1
0
Reserved
1
1
Internal 2.56V Voltage Reference with external capacitor on AREF pin
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data
Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right
adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,
regardless of any ongoing conversions. For a complete description of this bit, see “The
ADC Data Register – ADCL and ADCH” on page 282.
• Bits 4:0 – MUX4:0: Analog Channel Selection Bits
The value of these bits selects which combination of analog inputs are connected to the
ADC. These bits also select the gain for the differential channels. See Table 102 for
details. If these bits are changed during a conversion, the change will not go in effect
until this conversion is complete (ADIF in ADCSRA is set).
4250E–CAN–12/04
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