MEGA128CAN Datasheet, PDF (180/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRBn is written to
one, the USARTn Data Register Empty Interrupt will be executed as long as UDREn is
set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn.
When interrupt-driven data transmission is used, the Data Register Empty interrupt rou-
tine must either write new data to UDRn in order to clear UDREn or disable the Data
Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine
terminates.
The Transmit Complete (TXCn) flag bit is set one when the entire frame in the Transmit
Shift Register has been shifted out and there are no new data currently present in the
transmit buffer. The TXCn flag bit is automatically cleared when a transmit complete
interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn
flag is useful in half-duplex communication interfaces (like the RS-485 standard), where
a transmitting application must enter receive mode and free the communication bus
immediately after completing the transmission.
When the Transmit Complete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the
USARTn Transmit Complete Interrupt will be executed when the TXCn flag becomes
set (provided that global interrupts are enabled). When the transmit complete interrupt is
used, the interrupt handling routine does not have to clear the TXCn flag, this is done
automatically when the interrupt is executed.
Parity Generator
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is
enabled (UPMn1 = 1), the transmitter control logic inserts the parity bit between the last
data bit and the first stop bit of the frame that is sent.
Disabling the Transmitter
The disabling of the Transmitter (setting the TXENn to zero) will not become effective
until ongoing and pending transmissions are completed, i.e., when the Transmit Shift
Register and Transmit Buffer Register do not contain data to be transmitted. When dis-
abled, the Transmitter will no longer override the TxDn pin.
Data Reception – USART
Receiver
The USARTn Receiver is enabled by writing the Receive Enable (RXENn) bit in the
UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of
the RxDn pin is overridden by the USARTn and given the function as the Receiver’s
serial input. The baud rate, mode of operation and frame format must be set up once
before any serial reception can be done. If synchronous operation is used, the clock on
the XCKn pin will be used as transfer clock.
Receiving Frames with 5 to 8
Data Bits
The Receiver starts data reception when it detects a valid start bit. Each bit that follows
the start bit will be sampled at the baud rate or XCKn clock, and shifted into the Receive
Shift Register until the first stop bit of a frame is received. A second stop bit will be
ignored by the Receiver. When the first stop bit is received, i.e., a complete serial frame
is present in the Receive Shift Register, the contents of the Shift Register will be moved
into the receive buffer. The receive buffer can then be read by reading the UDRn I/O
location.
180 AT90CAN128
4250E–CAN–12/04