MEGA128CAN Datasheet, PDF (129/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
Figure 58. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 59 shows the count sequence close to TOP in various modes. When using phase
and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The
timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by
BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn flag at
BOTTOM.
Figure 59. Timer/Counter Timing Diagram, no Prescaling
clk_I/O
clk_Tn
(clk_I/O/1)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TOP - 1
TOP - 1
TOP
TOP
Old OCRnx Value
BOTTOM
TOP - 1
BOTTOM + 1
TOP - 2
New OCRnx Value
Figure 60 shows the same timing data, but with the prescaler enabled.
4250E–CAN–12/04
129