MEGA128CAN Datasheet, PDF (235/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

CAN Channel
Configuration
Bit Timing
AT90CAN128
The CAN channel can be in:
• Enabled mode
In this mode:
– the CAN channel (internal TXDCAN & RXDCAN) is enabled,
– the input clock is enabled.
• Standby mode
In standby mode:
– the transmitter constantly provides a recessive level (on internal TXDCAN)
and the receiver is disabled,
– input clock is enabled,
– the registers and pages remain accessible.
• Listening mode
This mode is transparent for the CAN channel:
– enables a hardware loop back, internal TXDCAN on internal RXDCAN
– provides a recessive level on TXDCAN pin
– does not disable RXDCAN
– freezes TEC and REC error counters
Figure 116. Listening Mode
internal
TXDcan
LISTEN
internal
1
RXDcan
0
PD5 _TXDcan
PD6 _RXDcan
FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time
quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s.
Field and segment abbreviations:
• BRP: Baud Rate Prescaler.
• TQ: Time Quantum (output of Baud Rate Prescaler).
• SYNS: SYNchronization Segment is 1 TQ long.
• PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long.
• PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.
• PHS2: PHase Segment 2 is programmable to be maximum of PHS1 and
INFORMATION PROCESSING TIME.
• INFORMATION PROCESSING TIME is 2 TQ.
• SJW: (Re) Synchronization Jump Width is programmable to be minimum of PHS1
and 4.
The total number of TQ in a bit time has to be programmed at least from 8 to 25.
4250E–CAN–12/04
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