MEGA128CAN Datasheet, PDF (205/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

Overview of the TWI
Module
AT90CAN128
The TWI module is comprised of several submodules, as shown in Figure 98. All regis-
ters drawn in a thick line are accessible through the AVR data bus.
Figure 98. Overview of the TWI Module
SCL
Slew-rate Spike
Control
Filter
SDA
Slew-rate Spike
Control
Filter
Bus Interface Unit
START / STOP
Control
Spike Suppression
Arbitration detection
Address/Data Shift
Register (TWDR)
Ack
Bit Rate Generator
Prescaler
Bit Rate Register
(TWBR)
Scl and SDA Pins
Bit Rate Generator Unit
4250E–CAN–12/04
Address Match Unit
Address Register
(TWAR)
Address Comparator
Control Unit
Status Register
(TWSR)
Control Register
(TWCR)
State Machine and
Status control
TWI
Unit
These pins interface the AVR TWI with the rest of the MCU system. The output drivers
contain a slew-rate limiter in order to conform to the TWI specification. The input stages
contain a spike suppression unit removing spikes shorter than 50 ns. Note that the inter-
nal pullups in the AVR pads can be enabled by setting the PORT bits corresponding to
the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in
some systems eliminate the need for external ones.
This unit controls the period of SCL when operating in a Master mode. The SCL period
is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in
the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Pres-
caler settings, but the CPU clock frequency in the slave must be at least 16 times higher
than the SCL frequency. Note that slaves may prolong the SCL low period, thereby
reducing the average TWI bus clock period. The SCL frequency is generated according
to the following equation:
SCL frequency = -₁---₆-----+-----₂---₍--_T---^C-_W---^L---_B-^K---_R-ⁱ-^o--₎---_â‹---₄----_T---_W----_P----_S
• TWBR = Value of the TWI Bit Rate Register
• TWPS = Value of the prescaler bits in the TWI Status Register
Note:
TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than
10, the master may produce an incorrect output on SDA and SCL for the reminder of the
byte. The problem occurs when operating the TWI in Master mode, sending Start + SLA
+ R/W to a slave (a slave does not need to be connected to the bus for the condition to
happen).
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