MEGA128CAN Datasheet, PDF (168/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

SPI Status Register – SPSR
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written
logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will
be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to Figure 81 and Figure 82 for an example. The CPOL func-
tionality is summarized below:
Table 72. CPOL Functionality
CPOL
0
1
Leading Edge
Rising
Falling
Trailing Edge
Falling
Rising
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to Figure 81 and Figure 82 for an example.
The CPOL functionality is summarized below:
Table 73. CPHA Functionality
CPHA
0
1
Leading Edge
Sample
Setup
Trailing Edge
Setup
Sample
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the clk_IO fre-
quency f_clkio is shown in the following table:
Table 74. Relationship Between SCK and the Oscillator Frequency
SPI2X
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
SCK Frequency
f_clkio/4
f_clkio/16
f_clkio/64
f_clkio/128
f_clkio/2
f_clkio/8
f_clkio/32
f_clkio/64
Bit
7
6
5
4
3
2
1
0
SPIF WCOL
–
–
–
–
–
SPI2X
SPSR
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
168 AT90CAN128
4250E–CAN–12/04