MEGA128CAN Datasheet, PDF (365/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

External Data Memory Characteristics
AT90CAN128
Table 142. External Data Memory Characteristics, V_CC = 4.5 - 5.5 Volts, No Wait-state
8 MHz Oscillator
Variable Oscillator
Symbol Parameter
Min.
Max.
Min.
Max.
0
1/t_CLCL
Oscillator Frequency
0.0
16
1
t_LHLL
ALE Pulse Width
115
1.0 t_CLCL – 10
2
t_AVLL
Address Valid A to ALE Low
57.5
0.5 t_CLCL – 5 ⁽¹⁾
3a
t_{LLAX_ST}
Address Hold After ALE Low,
write access
5
5
3b
t_{LLAX_LD}
4
t_AVLLC
Address Hold after ALE Low,
read access
Address Valid C to ALE Low
5
57.5
5
0.5 t_CLCL – 5 ⁽¹⁾
5
t_AVRL
Address Valid to RD Low
115
1.0 t_CLCL – 10
6
t_AVWL
7
t_LLWL
Address Valid to WR Low
ALE Low to WR Low
115
47.5
67.5
1.0 t_CLCL – 10
0.5 t_CLCL – 15 ⁽²⁾
0.5 t_CLCL + 5 ⁽²⁾
8
t_LLRL
ALE Low to RD Low
47.5
67.5
0.5 t_CLCL – 15 ⁽²⁾
0.5 t_CLCL + 5 ⁽²⁾
9
t_DVRH
Data Setup to RD High
40
40
10 t_RLDV
Read Low to Data Valid
75
1.0 t_CLCL – 50
11 t_RHDX
Data Hold After RD High
0
0
12 t_RLRH
13 t_DVWL
RD Pulse Width
Data Setup to WR Low
115
42.5
1.0 t_CLCL – 10
0.5 t_CLCL – 20 ⁽¹⁾
14 t_WHDX
Data Hold After WR High
115
1.0 t_CLCL – 10
15 t_DVWH
Data Valid to WR High
125
1.0 t_CLCL
16 t_WLWH
WR Pulse Width
115
1.0 t_CLCL – 10
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4250E–CAN–12/04
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