MEGA128CAN Datasheet, PDF (62/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

Ports as General Digital
I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 31 shows a
functional description of one I/O-port pin, here generically called Pxn.
Figure 31. General Digital I/O⁽¹⁾
Configuring the Pin
QD
DDxn
Q _CLR
RESET
PUD
WDx
RDx
1
Pxn
QD
PORTxn
0
SLEEP
Q _CLR
RESET
RRx
WPx
WRx
SYNCHRONIZER
DQ
LQ
DQ
PINxn
Q
RPx
clk _I/O
PUD: PULLUP DISABLE
SLEEP: SLEEP CONTROL
clk_I/O : I/O CLOCK
WDx: WRITE DDRx
RDx: READ DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
WPx: WRITE PINx REGISTER
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clk_I/O, SLEEP, and PUD are common to all ports.
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
“Register Description for I/O-Ports” on page 85, the DDxn bits are accessed at the
DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at
the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written
logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-
ured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up
resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic
zero or the pin has to be configured as an output pin
The port pins are tri-stated when reset condition becomes active, even if no clocks are
running.
62 AT90CAN128
4250E–CAN–12/04