MEGA128CAN Datasheet, PDF (319/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
the Page Erase and Page Write operation is addressing the same page. See “Simple
Assembly Code Example for a Boot Loader” on page 321 for an assembly code
example.
Performing Page Erase by
SPM
To execute Page Erase, set up the address in the Z-pointer/RAMPZ, write “X0000011”
to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data
in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register
and RAMPZ. Other bits in the Z-pointer must be written zero during this operation.
• Page Erase to the RWW section: The NRWW section can be read during the page
erase.
• Page Erase to the NRWW section: The CPU is halted during the operation.
Filling the Temporary Buffer
(Page Loading)
To write an instruction word, set up the address in the Z-pointer/RAMPZ and data in
R1:R0, write “00000001” to SPMCSR and execute SPM within four clock cycles after
writing SPMCSR. The content of PCWORD in the Z-register is used to address the data
in the temporary buffer. The temporary buffer will auto-erase after a Page Write opera-
tion or by writing the RWWSRE bit in SPMCSR. It is also erased after a system reset.
Note that it is not possible to write more than one time to each address without erasing
the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded
will be lost.
Performing a Page Write
To execute Page Write, set up the address in the Z-pointer/RAMPZ, write “X0000101” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in
R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the
Z-pointer will be ignored during this operation.
• Page Write to the RWW section: The NRWW section can be read during the Page
Write.
• Page Write to the NRWW section: The CPU is halted during the operation.
Using the SPM Interrupt
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt
when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used
instead of polling the SPMCSR Register in software. When using the SPM interrupt, the
Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is
accessing the RWW section when it is blocked for reading. How to move the interrupts
is described in “Interrupts” on page 56.
Consideration While Updating
BLS
Special care must be taken if the user allows the Boot Loader section to be updated by
leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can
corrupt the entire Boot Loader, and further software updates might be impossible. If it is
not necessary to change the Boot Loader software itself, it is recommended to program
the Boot Lock bit11 to protect the Boot Loader software from any internal software
changes.
Prevent Reading the RWW
Section During Self-
Programming
During Self-Programming (either Page Erase or Page Write), the RWW section is
always blocked for reading. The user software itself must prevent that this section is
addressed during the self programming operation. The RWWSB in the SPMCSR will be
set as long as the RWW section is busy. During Self-Programming the Interrupt Vector
table should be moved to the BLS as described in “Interrupts” on page 56, or the inter-
rupts must be disabled. Before addressing the RWW section after the programming is
completed, the user software must clear the RWWSB by writing the RWWSRE. See
“Simple Assembly Code Example for a Boot Loader” on page 321 for an example.
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