MEGA128CAN Datasheet, PDF (137/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
Input Capture Register –
ICR3H and ICR3L
Timer/Counter1 Interrupt
Mask Register – TIMSK1
Timer/Counter3 Interrupt
Mask Register – TIMSK3
4250E–CAN–12/04
Initial Value
0
0
0
0
0
0
0
0
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
ICR3[15:8]
ICR3H
ICR3[7:0]
ICR3L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Input Capture is updated with the counter (TCNTn) value each time an event occurs
on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1).
The Input Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is
shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 111
Bit
7
6
5
4
3
2
1
0
–
–
ICIE1
–
OCIE1C OCIE1B OCIE1A TOIE1 TIMSK1
Read/Write
R
R
R/W
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
–
–
ICIE3
–
OCIE3C OCIE3B OCIE3A TOIE3 TIMSK3
Read/Write
R
R
R/W
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICIEn: Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 56 ) is executed when the ICFn
flag, located in TIFRn, is set.
• Bit 4 – Reserved Bit
This bit is reserved for future use.
• Bit 3 – OCIEnC: Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 56 ) is executed when the
OCFnC flag, located in TIFRn, is set.
• Bit 2 – OCIEnB: Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 56 ) is executed when the
OCFnB flag, located in TIFRn, is set.
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