MEGA128CAN Datasheet, PDF (269/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

4250E–CAN–12/04
AT90CAN128
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the con-
version starts at the following rising edge of the ADC clock cycle. See “Differential
Channels” on page 270 for details on differential conversion timing.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is
switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize
the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal
conversion and 13.5 ADC clock cycles after the start of an first conversion. When a con-
version is complete, the result is written to the ADC Data Registers, and ADIF is set. In
Single Conversion mode, ADSC is cleared simultaneously. The software may then set
ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This
assures a fixed delay from the trigger event to the start of conversion. In this mode, the
sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conver-
sion completes, while ADSC remains high. For a summary of conversion times, see
Table 99.
Figure 130. ADC Timing Diagram, First Conversion (Single Conversion Mode)
First Conversion
Next
Conversion
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
1
2
12 13 14 15 16 17 18 19 20 21 22 23 24 25
1
2
3
MUX and REFS
Update
Sample & Hold
Conversion
Complete
Sign and MSB of Result
LSB of Result
MUX
and REFS
Update
Figure 131. ADC Timing Diagram, Single Conversion
One Conversion
Next Conversion
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
1
2
3
4
5
6
7
8
9
10 11 12 13
123
Sample & Hold
MUX and REFS
Update
Conversion
Complete
Sign and MSB of Result
LSB of Result
MUX and REFS
Update
269