AMD-K6-2E Datasheet, PDF (75/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
s reg16/32—word or doubleword integer register defined by
instruction byte(s) or bits 5, 4, and 3 of the modR/M byte
Opcode Bytes
The second and third columns list all applicable opcode bytes.
ModR/M Byte
The fourth column lists the modR/M byte when used by the
instruction. The modR/M byte defines the instruction as a
register or memory form. If modR/M bits 7 and 6 are documented
as mm (memory form), mm can only be 10b, 01b or 00b.
Decode Type
The fifth column lists the type of instruction decode — short,
long, and vector. The AMD-K6-2E processor decode logic can
process two short, one long, or one vector decode per clock.
RISC86 Operation
The sixth column lists the type of RISC86 operation(s) required
for the instruction. The operation types and corresponding
execution units are as follows:
s alu—either of the integer execution units
s alux—integer X execution unit only
s branch—branch condition unit
s float—floating-point execution unit
s limm—load immediate, instruction control unit
s load, fload, mload—load unit
s meu—Multimedia execution units for MMX and 3DNow!
instructions
s store, fstore, mstore—store unit
Table 12. Integer Instructions
Instruction Mnemonic
AAA
AAD
AAM
AAS
ADC mreg8, reg8
ADC mem8, reg8
ADC mreg16/32, reg16/32
ADC mem16/32, reg16/32
ADC reg8, mreg8
ADC reg8, mem8
First Second
Byte Byte
37h
D5h
0Ah
D4h
0Ah
3Fh
10h
10h
11h
11h
12h
12h
ModR/M
Byte
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
Decode RISC86
Type Operations
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
Chapter 3
Software Environment
57