AMD-K6-2E Datasheet, PDF (267/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
13.2
Halt State
Enter Halt State
During the execution of the HLT instruction, the AMD-K6-2E
processor executes a Halt special cycle. After BRDY# is
sampled asserted during this cycle, and then EWBE# is also
sampled asserted (if not masked off), the processor enters the
Halt state in which the processor disables most of its internal
clock distribution.
To support the following operations, the internal phase-lock
loop (PLL) continues to run, and some internal resources are
still clocked in the Halt state:
s Inquire Cycles—The processor continues to sample AHOLD,
BOFF#, and HOLD to support inquire cycles that are
initiated by the system logic. The processor transitions to
the Stop Grant Inquire state during the inquire cycle. After
returning to the Halt state following the inquire cycle, the
processor does not execute another Halt special cycle.
s Flush Cycles—The processor continues to sample FLUSH#.
If FLUSH# is sampled asserted, the processor performs the
flush operation in the same manner as it is performed in the
Normal state. Upon completing the flush operation, the
processor executes the Halt special cycle which indicates
the processor is in the Halt state.
s Time Stamp Counter (TSC)—The TSC continues to count in
the Halt state.
s Signal Sampling—The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
Exit Halt State
After entering the Halt state, all signals driven by the processor
retain their state as they existed following the completion of
the Halt special cycle.
The AMD-K6-2E processor remains in the Halt state until it
samples INIT, INTR (if interrupts are enabled), NMI, RESET, or
SMI# asserted. If any of these signals is sampled asserted, the
processor returns to the Normal state and performs the
corresponding operation. All of the normal requirements for
recognition of these input signals apply within the Halt state.
Chapter 13
Clock Control
249