AMD-K6-2E Datasheet, PDF (215/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
9. Between 15–16 Mbytes—If the address of a pending write
cycle is in the 1 Mbyte of memory between 15 Mbytes and 16
Mbytes, and the WAE15M bit is 1, write allocate for this
cycle is enabled.
10. Write Allocate Enable 15–16 Mbytes (WAE15M)—This
condition is associated with the Write Allocate Limit
mechanism and affects write allocate only if the limit
specified by the WAELIM field is greater than or equal to
16 Mbytes. If the memory address is between 15 Mbytes and
16 Mbytes, and the WAE15M bit in the WHCR is 0, write
allocate for this cycle is disabled (even if condition 10
attempts to prevent write allocate, condition 5 or 6 allows
write allocate to occur).
8.8
Prefetching
Hardware
Prefetching
Software Prefetching
The AMD-K6-2E processor conditionally performs cache
prefetching which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
burst read cycles occurring back-to-back or, if allowed, as
pipelined cycles. The burst read cycles do not occur
back-to-back (wait states occur) if the processor is not ready to
start a new cycle, if higher priority data read or write requests
exist, or if NA# (next address) was sampled negated. Wait states
can also exist between burst cycles if the processor samples
AHOLD or BOFF# asserted.
The 3DNow! technology includes an instruction called
PREFETCH that allows a cache line to be prefetched into the
L1 data cache. Unlike prefetching under hardware control,
software prefetching only fetches the cache line specified by
the operand of the PREFETCH instruction, and does not
attempt to fetch the other cache line in the sector. The
PREFETCH instruction format is defined in Table 15,
“3DNow!™ Instructions,” on page 81. For more detailed
information, see the 3DNow!™ Technology Manual, order#
21928.
Chapter 8
Cache Organization
197