AMD-K6-2E Datasheet, PDF (258/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
12.5
the execution of writeback cycles when a modified cache line is
hit.
While the L1 is inhibited, the processor continues to drive the
PCD output signal appropriately, which system logic can use to
control external L2 caching.
In order to completely disable the L1 cache so that no valid
lines exist in the cache, the Cache Inhibit bit must be set to 1
and the cache must be flushed in one of the following ways:
s By asserting the FLUSH# input signal
s By executing the WBINVD instruction
s By executing the INVD instruction (modified cache lines are
not written back to memory)
s By using the Page Flush/Invalidate register (PFIR) (see
“Page Flush/Invalidate Register (PFIR)” on page 200)
Debug
The AMD-K6-2E processor implements the standard x86 debug
functions, registers, and exceptions. In addition, the processor
supports the I/O breakpoint debug extension. The debug
feature assists programmers and system designers during
software execution tracing by generating exceptions when one
or more events occur during processor execution. The exception
handler, or debugger, can be written to perform various tasks,
such as displaying the conditions that caused the breakpoint to
occur, displaying and modifying register or memory contents, or
single-stepping through program execution.
The following sections describe the debug registers and the
various types of breakpoints and exceptions that the processor
supports.
240
Test and Debug
Chapter 12