AMD-K6-2E Datasheet, PDF (138/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
5.42
SCYC (Split Cycle)
Pin Attribute
Output
Pin Location
Summary
AL-17
The processor asserts SCYC during misaligned, locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
For purposes of bus cycles, the term aligned means:
s Any 1-byte transfers
s 2-byte and 4-byte transfers that lie within 4-byte address
boundaries
s 8-byte transfers that lie within 8-byte address boundaries
Driven and Floated
SCYC is asserted off the same clock edge as ADS#, and negated
off the clock edge on which NA# or the last expected BRDY# of
the entire locked sequence is sampled asserted. SCYC is only
valid during locked memory cycles.
SCYC is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge on which the processor asserts
HLDA in response to HOLD.
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Signal Descriptions
Chapter 5