AMD-K6-2E Datasheet, PDF (257/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
12.4
The following states have no effect on the normal or test
operation of the processor other than as shown in Figure 82 on
page 237:
s Run-Test/Idle—This state is an idle state between scan
operations.
s Select-DR-Scan—This is the initial state of the test data
register state transitions.
s Select-IR-Scan—This is the initial state of the Instruction
Register state transitions.
s Exit1-DR—This state is entered to terminate the shifting
process and enter the Update-DR state.
s Exit1-IR—This state is entered to terminate the shifting
process and enter the Update-IR state.
s Pause-DR—This state is entered to temporarily stop the
shifting process of a test data register.
s Pause-IR—This state is entered to temporarily stop the
shifting process of the instruction register.
s Exit2-DR—This state is entered in order to either terminate
the shifting process and enter the Update-DR state or to
resume shifting following the exit from the Pause-DR state.
s Exit2-IR—This state is entered in order to either terminate
the shifting process and enter the Update-IR state or to
resume shifting following the exit from the Pause-IR state.
L1 Cache Inhibit
The AMD-K6-2E processor provides a means for inhibiting the
normal operation of its L1 instruction and data caches while
still supporting an external level-2 (L2) cache. This capability
allows system designers to disable the L1 cache during the
testing and debug of an L2 cache.
If the Cache Inhibit bit (bit 3) of test register 12 (TR12) is 0, the
processor’s L1 cache is enabled and operates as described in
“Cache Organization” on page 185. If the Cache Inhibit bit is 1,
the L1 cache is disabled and no new cache lines are allocated.
Even though new allocations do not occur, valid L1 cache lines
remain valid and are read by the processor when a requested
address hits a cache line. In addition, the processor continues to
support inquire cycles initiated by the system logic, including
Chapter 12
Test and Debug
239