AMD-K6-2E Datasheet, PDF (265/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
13 Clock Control
13.1
Clock Control States
The AMD-K6-2E processor supports five modes of clock control.
The processor can transition between these modes to maximize
performance, to minimize power dissipation, or to provide a
balance between performance and power. (See “Power
Dissipation” on page 258 for the maximum power dissipation of
t h e A M D -K 6 -2 E p ro c e s s o r w it h in t h e n o r m a l a n d t h e
reduced-power states.)
The five clock-control states supported are:
s Normal State—The processor is running in real mode,
virtual-8086 mode, protected mode, or system management
mode (SMM). In this state, all clocks are running— including
the external bus clock, CLK, and the internal processor
clock—and the full features and functions of the processor
are available.
s Halt State—This low-power state is entered following the
successful execution of the HLT instruction. During this
state, the internal processor clock is stopped.
s Stop Grant State—This low-power state is entered following
the recognition of the assertion of the STPCLK# signal.
During this state, the internal processor clock is stopped.
s Stop Grant Inquire State—This state is entered from the
Halt state and the Stop Grant state as the result of a
system-initiated inquire cycle.
s Stop Clock State—This low-power state is entered from the
Stop Grant state when the CLK signal is stopped.
Figure 87 on page 248 illustrates the clock control state
transitions. Each of the four reduced-power states are described
in the following sections.
Chapter 13
Clock Control
247