AMD-K6-2E Datasheet, PDF (121/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
5.22
FERR# (Floating-Point Error)
Pin Attribute
Output
Pin Location
Summary
Q-05
The assertion of FERR # indicates the occurrence of an
unmasked floating-point exception resulting from the
execution of a floating-point instruction. This signal is provided
to allow the system logic to handle this exception in a manner
consistent with IBM-compatible PC/AT systems. See “Handling
Floating-Point Exceptions” on page 213 for a system logic
implementation that supports floating-point exceptions.
The state of the numeric error (NE) bit in CR0 does not affect
the FERR # signal.
Driven
The processor is designed so that FERR # does not glitch,
enabling the signal to be used as a clocking source for system
logic.
The processor asserts FERR # on the instruction boundary of
the next floating-point instruction, MMX instruction, 3DNow!
instruction, or WAIT instruction that occurs following the
fl o a t i ng -po i nt i ns tr u c ti o n t h a t c a u s e d th e u n ma s ke d
floating-point exception—that is, FERR# is not asserted at the
time the exception occurs. The IGNNE# signal does not affect
the assertion of FERR#.
FERR # is negated during the following conditions:
s Following the successful execution of the floating-point
instructions FCLEX, FINIT, FSAVE, and FSTENV
s Under certain circumstances, following the successful
execution of the floating-point instructions FLDCW,
FLDENV, and FRSTOR, which load the floating-point status
word or the floating-point control word
s Following the falling transition of RESET
FERR # is always driven except in the three-state test mode.
See “IGNNE# (Ignore Numeric Exception)” on page 108 for
more details on floating-point exceptions.
Chapter 5
Signal Descriptions
103