AMD-K6-2E Datasheet, PDF (212/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
Write Handling Control Register (WHCR) . Th e W H C R re g i s t e r
contains two fields —the Write Allocate Enable Limit
(WAELIM) field, and the Write Allocate Enable 15-to-16-Mbyte
(WAE15M) bit (see Figure 76).
63
32 31
22 21 17 16 15
0
W
A
WAELIM
E
1
5
M
Reserved
Symbol
WAELIM
WAE15M
Description
Bits
Write Allocate Enable Limit
31-22
Write Allocate Enable 15-to-16-Mbyte 16
Note: Hardware RESET initializes this MSR to all zeros.
Figure 76. Write Handling Control Register (WHCR)
Write Allocate Enable Limit Field. The WAELIM field is 10 bits wide.
This field, multiplied by 4 Mbytes, defines an upper memory
limit. Any pending write cycle that addresses memory below
this limit causes the processor to perform a write allocate
(assuming the address is not within a range where write
allocates are disallowed). Write allocate is disabled for memory
accesses at and above this limit unless the processor determines
a pending write cycle is cacheable by means of one of the other
write allocate mechanisms—“Write to a Cacheable Page” and
“Write to a Sector.” The maximum value of this limit is ((2¹⁰–1)
· 4 Mbytes) = 4092 Mbytes. When all the bits in this field are 0,
all memory is above this limit and the write allocate mechanism
is disabled (even if all bits in the WAELIM field are 0, write
allocates can still occur due to the “Write to a Cacheable Page”
and “Write to a Sector” mechanisms).
Write Allocate Enable 15-to-16-Mbyte Bit. The Write Allocate Enable
1 5-t o -1 6 -M by t e ( WA E1 5 M) b it i s u se d t o e n able w r it e
allocations for the memory write cycles that address the 1
Mbyte of memory between 15 Mbytes and 16 Mbytes. This bit
must be set to 1 to allow write allocate in this memory area. This
bit is provided to account for a small number of uncommon
memory-mapped I/O adapters that use this particular memory
address space. If the system contains one of these peripherals,
the bit should be written to 0 (even if the WAE15M bit is 0,
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Cache Organization
Chapter 8