AMD-K6-2E Datasheet, PDF (237/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
Table 40 shows the initial state of registers when entering SMM.
Table 40. Initial State of Registers in System Management Mode (SMM)
Register
SMM Initial State
General-Purpose Registers Unmodified
EFLAGs
0000_0002h
CR0
PE, EM, TS, and PG are cleared (bits 0, 2, 3, and 31).
The other bits are unmodified.
DR7
0000_0400h
GDTR, LDTR, IDTR, TSSR, DR6 Unmodified
EIP
0000_8000h
CS
0003_0000h
DS, ES, FS, GS, SS
0000_0000h
11.2
SMM State-Save Area
When the processor acknowledges an SMI# interrupt by
asserting SMIACT#, it saves its state in a 512-byte SMM
state-save area shown in Table 41. The save begins at the top of
the SMM memory area (SMM base address + FFFFh) and fills
down to SMM base address + FE00h.
Table 41 shows the offsets in the SMM state-save area relative
to the SMM base address. The SMM service routine can alter
any of the read/write values in the state-save area.
Table 41. SMM State-Save Area Map
Address Offset
FFFCh
FFF8h
FFF4h
FFF0h
FFECh
FFE8h
FFE4h
FFE0h
FFDCh
FFD8h
FFD4h
FFD0h
Contents Saved
CR0
CR3
EFLAGS
EIP
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
Chapter 11
System Management Mode (SMM)
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