AMD-K6-2E Datasheet, PDF (63/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
UC/WC Cacheability
Control Register
(UWCCR)
The AMD-K6-2E processor provides two variable-range Memory
Type Range Registers (MTRRs)—MTRR0 and MTRR1—that
each specify a range of memory. Each range can be defined as
uncacheable (UC) or write-combining (WC) memory. Figure 37
shows the format of the UWCCR register. For more detailed
information about the MTRR0, MTRR1, and UWCCR registers,
see “Memory Type Range Registers” on page 207.
.
Symbol Description
Bits
UC1 Uncacheable Memory Type 32
WC1 Write-Combining Memory Type 33
Symbol Description
Bits
UC0 Uncacheable Memory Type 0
WC0 Write-Combining Memory Type 1
63
49 48
34 33 32 31
17 16
2 10
Physical Base Address 1
WU
Physical Address Mask 1 C C
11
Physical Base Address 0
WU
Physical Address Mask 0 C C
00
MTRR1
MTRR0
Figure 37. UC/WC Cacheability Control Register (UWCCR)
Processor State
Observability
Register (PSOR)
The AMD-K6-2E processor provides the processor state
observability register (PSOR) (see Figure 38).
63
Reserved
Symbol
Description
Bit
NOL2 No L2 Functionality
8
STEP
Processor Stepping
7-4
BF
Bus Frequency Divisor
2-0
Figure 38. Processor State Observability Register (PSOR)
9 87
432
0
N
O
L
STEP
BF
2
Chapter 3
Software Environment
45