AMD-K6-2E Datasheet, PDF (139/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
5.43
SMI# (System Management Interrupt)
Pin Attribute
Pin Location
Summary
Input, Internal Pullup
AB-34
The assertion of SMI# causes the processor to enter system
management mode (SMM). Upon recognizing SMI#, the
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycles
3. Acknowledges the interrupt by asserting SMIACT# after
sampling EWBE# asserted (if EWBE# is masked off, then
SMIACT# is not affected by EWBE#)
4. Saves the internal processor state in SMM memory
5. Disables interrupts by clearing the interrupt flag (IF) in
EFLAGS and disables NMI interrupts
6. Jumps to the entry point of the SMM service routine at the
SMM base physical address which defaults to 0003_8000h in
SMM memory
See “System Management Mode (SMM)” on page 217 for more
details regarding SMM.
Sampled
SMI# is sampled and latched as a falling edge-sensitive signal.
SMI# is sampled on every clock edge but is not recognized until
the next instruction boundary. If SMI# is to be recognized on
the instruction boundary associated with a BRDY#, it must be
sampled asserted a minimum of three clock edges before the
BRDY# is sampled asserted. If it is asserted synchronously, it
can be asserted for a minimum of one clock. If it is asserted
asynchronously, it must have been negated for a minimum of
two clocks followed by an assertion of a minimum of two clocks.
A second assertion of SMI# while in SMM is latched but is not
recognized until the SMM service routine is exited.
Chapter 5
Signal Descriptions
121