AMD-K6-2E Datasheet, PDF (221/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
Cache Snooping
Table 36 shows the conditions under which snooping occurs in
the AMD-K6-2E processor and the resources that are snooped.
Table 36. Snoop Action
Type of Event
Inquire Cycle
Internal Snoop
Type of Access
System Logic
Read
Miss
Instruction Cache
Read
Hit
Read
Miss
Data Cache
Read
Hit
Write
Miss
Write
Hit
Snooping Action
Instruction Cache
Yes¹
Data Cache
Yes¹
Not applicable
Yes²
Not applicable
No
Yes³
Not applicable
No
Not applicable
Yes³
Not applicable
No
Not applicable
Notes:
1. The processor’s response to an inquire cycle depends on the state of the INV input signal and the state of the cache line as
follows:
For the instruction cache, if INV is sampled negated, the line remains invalid or valid, but if INV is sampled asserted, the line is
invalidated.
For the data cache, if INV is sampled negated, valid lines remain in or transition to the Shared state, a modified data cache line
is written back before the line is marked shared (with HITM# asserted), and invalid lines remain invalid. For the data cache, if
INV is sampled asserted, the line is marked invalid. Modified lines are written back before invalidation.
2. If an internal snoop hits a modified line in the data cache, the line is written back and invalidated. Then the instruction cache
performs a burst read from memory.
3. If an internal snoop hits a line in the instruction cache, the instruction cache line is invalidated and the data-cache read or write
is performed from memory.
Chapter 8
Cache Organization
203