AMD-K6-2E Datasheet, PDF (119/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
The processor always floats DP[7:0] except when they are being
driven during a write cycle as described above. In addition,
DP[7:0] are floated off the clock edge that BOFF # is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
5.20
EADS# (External Address Strobe)
Pin Attribute
Input
Pin Location
Summary
AM-04
System logic asserts EADS # during a cache inquire cycle to
indicate that the address bus contains a valid address. EADS#
can only be driven after the system logic has taken control of
the address bus by asserting AHOLD or BOFF# or by receiving
HLDA. The processor responds to the sampling of EADS# and
the address bus by driving HIT#, which indicates if the inquired
cache line exists in the processor’s cache, and HITM#, which
indicates if it is in the modified state.
Sampled
If AHOLD or BOFF# is asserted by the system logic in order to
execute a cache inquire cycle, the processor begins sampling
EADS # two clock edges after AHOLD or BOFF # is sampled
asserted. If the system logic asserts HOLD in order to execute a
cache inquire cycle, the processor begins sampling EADS# two
clock edges after the clock edge HLDA is asserted by the
processor.
EADS # is ignored during the following conditions:
s One clock edge after the clock edge on which EADS# is
sampled asserted
s Two clock edges after the clock edge on which ADS# is
asserted
s When the processor is driving the address bus
s When the processor asserts HITM#
Chapter 5
Signal Descriptions
101