AMD-K6-2E Datasheet, PDF (126/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
5.28
IGNNE# (Ignore Numeric Exception)
Pin Attribute
Input
Pin Location
Summary
AA-35
IGNNE#, in conjunction with the numeric error (NE) bit in CR0,
is used by the system logic to control the effect of an unmasked
floating-point exception on a previous floating-point instruction
during the execution of a floating-point instruction, MMX
instruction, 3DNow! instruction, or the WAIT instruction—
hereafter referred to as the target instruction.
If an unmasked floating-point exception is pending and the
target instruction is considered error-sensitive, then the
relationship between NE and IGNNE# is as follows:
s If NE = 0, then:
• If IGNNE# is sampled asserted, the processor ignores the
floating-point exception and continues with the
execution of the target instruction.
• If IGNNE# is sampled negated, the processor waits until
it samples IGNNE#, INTR, SMI#, NMI, or INIT asserted.
If IGNNE# is sampled asserted while waiting, the
processor ignores the floating-point exception and
continues with the execution of the target instruction.
If INTR, SMI#, NMI, or INIT is sampled asserted while
waiting, the processor handles its assertion
appropriately.
s If NE = 1, the processor invokes the INT 10h exception
handler.
If an unmasked floating-point exception is pending and the
target instruction is considered error-insensitive, then the
processor ignores the floating-point exception and continues
with the execution of the target instruction.
FERR # is not affected by the state of the NE bit or IGNNE #.
FERR # is always asserted at the instruction boundary of the
target instruction that follows the floating-point instruction
that caused the unmasked floating-point exception.
108
Signal Descriptions
Chapter 5