AMD-K6-2E Datasheet, PDF (37/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
Register X and Y
Pipelines
Chapter 2
The Integer X execution unit can operate on all ALU
operations, multiplies, divides (signed and unsigned), shifts,
and rotates.
The Integer Y execution unit can operate on the basic word and
doubleword ALU operations — ADD, AND, CMP, OR, SUB,
XOR, zero-extend, and sign-extend operands.
Table 1. Execution Latency and Throughput of Execution Units
Functional Unit
Store
Load
Integer X
Multimedia
(processes
MMX instructions)
Integer Y
Branch
FPU
3DNow!
Function
LEA/PUSH, Address (Pipelined)
Memory Store (Pipelined)
Memory Loads (Pipelined)
Integer ALU
Integer Multiply
Integer Shift
MMX ALU
MMX Shifts, Packs, Unpack
MMX Multiply
Basic ALU (16-bit and 32-bit operands)
Resolves Branch Conditions
FADD, FSUB, FMUL
3DNow! ALU
3DNow! Multiply
3DNow! Convert
Latency
1
1
2
1
2–3
1
1
1
2
1
1
2
2
2
2
Throughput
1
1
1
1
2–3
1
1
1
1
1
1
2
1
1
1
The functional units that execute MMX and 3DNow!
instructions share pipeline control with the Integer X and
Integer Y units.
The register X and Y functional units are attached to the issue
bus for the register X execution pipeline or the issue bus for the
register Y execution pipeline or both. Each register pipeline
has dedicated resources that consist of an integer execution
unit and an MMX ALU execution unit, therefore allowing
superscalar operation on integer and MMX instructions. In
addition, both the X and Y issue buses are connected to the
3DNow! ALU, the MMX/3DNow! multiplier, and MMX shifter,
which allows the appropriate RISC86 operation to be issued
through either bus. Figure 6 on page 20 shows the details of the
X and Y register pipelines.
Internal Architecture
19