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AMD-K6-2E Datasheet, PDF (117/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor | |||
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22529B/0âJanuary 2000
Preliminary Information
AMD-K6â¢-2E Processor Data Sheet
5.18
D[63:0] (Data Bus)
Pin Attribute
Pin Location
Summary
Bidirectional
See âPin Designations by Functional Groupingâ on page 301.
D[63:0] represent the processorâs 64-bit data bus. Each of the
eight bytes of data that comprise this bus is qualified as valid
by its corresponding byte enable. See âBE[7:0]# (Byte
Enables)â on page 92.
Driven, Sampled, and
Floated
As Outputs: For single-transfer write cycles, the processor drives
D[63:0] with valid data one clock edge after the clock edge on
which ADS# is asserted and D[63:0] remain in the same state
until the clock edge on which BRDY# is sampled asserted. If the
cycle is a writebackâin which case four, 8-byte transfers
occurâD[63:0] are driven one clock edge after the clock edge
on which ADS# is asserted and are subsequently changed off
the clock edge on which each BRDY# assertion of the burst
cycle is sampled.
If the assertion of ADS# represents a pipelined write cycle that
follows a read cycle, the processor does not drive D[63:0] until it
is certain that contention on the data bus will not occur. In this
case, D[63:0] are driven the clock edge after the last expected
BRDY # of the previous cycle is sampled asserted.
As Inputs: During read cycles, the processor samples D[63:0] on
the clock edge on which BRDY# is sampled asserted.
The processor always floats D[63:0] except when they are being
driven during a write cycle as described above. In addition,
D[63:0] are floated off the clock edge that BOFF # is sampled
asserted and off the clock edge that the processor asserts
HLDA in recognition of HOLD.
Chapter 5
Signal Descriptions
99
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