AMD-K6-2E Datasheet, PDF (209/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
8.5
Cache-Line Fills
The processor performs a cache-line fill for any area of system
memory defined as cacheable. If an area of system memory is
not explicitly defined as uncacheable by the software or system
logic, or implicitly treated as uncacheable by the processor,
then the memory access is assumed to be cacheable.
Software can prevent caching of certain pages by setting the
PCD bit in the page directory entry (PDE) or page table entry
(PTE). Additionally, software can define regions of memory as
uncacheable or write combinable by programming the MTRRs
in the UC/WC cacheability control register (UWCCR) (see
“Memory Type Range Registers” on page 207). Write-
combinable memory is defined as uncacheable.
The system logic also has control of the cacheability of bus
cycles. If system logic determines the address is not cacheable,
system logic negates the KEN# signal when asserting the first
BRDY# or NA# of a cycle.
The processor does not cache certain memory accesses, such as
locked operations. In addition, the processor does not cache
PDE or PTE memory reads in the L1 cache (referred to as page
table walks).
When the processor needs to read memory, the processor drives
a read cycle onto the bus. If the cycle is cacheable, the
processor asserts CACHE#. If the cycle is not cacheable, a
non-burst, single-transfer read takes place. The processor waits
for the system logic to return the data and assert a single
BRDY# (See Figure 52 on page 139). If the cycle is cacheable,
the processor executes a 32-byte burst read cycle. The processor
expects a total of four BRDY# signals for a burst read cycle to
take place (See Figure 54 on page 143).
Cache-line fills initiate 32-byte burst read cycles from memory
on the system bus for the instruction cache and the data cache.
If a data-cache line being filled replaces a modified line, the
modified contents of the line are copied to a 32-byte writeback
(copyback) buffer in the bus interface unit while the new line is
being read.
Chapter 8
Cache Organization
191