AMD-K6-2E Datasheet, PDF (136/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
5.40
RESET (Reset)
Pin Attribute
Pin Location
Summary
Input
AK-20
When the processor samples RESET asserted, it immediately
flushes and initializes all internal resources and its internal
state including its pipelines and caches, the floating-point
state, the MMX state, the 3DNow! state, and all registers, and
then the processor jumps to address FFFF_FFF0h to start
instruction execution.
The FLUSH# signal is sampled during the falling transition of
RESET to invoke the three-state test mode.
Sampled
RESET is sampled as a level-sensitive input on every clock
edge. System logic can drive the signal either synchronously or
asynchronously.
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and V_CC
reach specification before it is negated.
During a warm reset, while CLK and V_CC are within their
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
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Signal Descriptions
Chapter 5