AMD-K6-2E Datasheet, PDF (222/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
8.11
8.12
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Writethrough and Writeback Coherency States
The terms writethrough and writeback apply to two related
concepts in a read-write cache like the AMD-K6-2E processor’s
L1 data cache. The following conditions apply to both the
writethrough and writeback modes:
s Memory Writes—A relationship exists between external
memory writes and their concurrence with cache updates:
• An external memory write that occurs concurrently with
a cache update to the same location is a writethrough.
Writethroughs are driven as single cycles on the bus.
• An external memory write that occurs after the processor
has modified a cache line is a writeback. Writebacks are
driven as burst cycles on the bus.
s Coherency State—A relationship exists between MESI
coherency states and writethrough-writeback coherency
states of lines in the cache as follows:
• Shared and invalid MESI lines are in writethrough state.
• Modified and exclusive MESI lines are in writeback state.
A20M# Masking of Cache Accesses
Although the processor samples A20M# as a level-sensitive
input on every clock edge, it should only be asserted in real
mode. The processor applies the A20M# masking to its tags,
through which all programs access the caches. Therefore,
assertion of A20M# affects all addresses (cache and external
memory), including the following:
s Cache-line fills (caused by read misses or write allocates)
s Cache writethroughs (caused by write misses or write hits to
lines in the Shared state)
However, A20M# does not mask writebacks or invalidations
caused by the following actions:
s Internal snoops
s Inquire cycles
s The FLUSH# signal
s The WBINVD instruction
s Writing to the page flush/invalidate register (PFIR)
Cache Organization
Chapter 8