AMD-K6-2E Datasheet, PDF (160/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
Burst Reads and
Pipelined Burst Reads
Figure 54 on page 143 shows normal burst read cycles and a
pipelined burst read cycle. The AMD-K6-2E processor drives
CACHE# and ADS# together to specify that the current bus
cycle is a burst cycle. If the processor samples KEN# asserted
with the first BRDY#, it performs burst transfers. During the
burst transfers, the system logic must ignore BE[7:0]# and must
return all eight bytes beginning at the starting address the
processor asserts on A[31:3]. Depending on the starting
address, the system logic must determine the successive
quadword addresses (A[4:3]) for each transfer in a burst, as
shown in Table 25. The processor expects the second, third, and
fourth quadwords to occur in the sequences shown in Table 25.
Table 25. A[4:3] Address-Generation Sequence During Bursts
Address Driven By
Processor on A[4:3]
A[4:3] Addresses of Subsequent
Quadwords¹ Generated by System Logic
Quadword 1
00b
01b
10b
11b
Quadword 2
01b
00b
11b
10b
Quadword 3
10b
11b
00b
01b
Quadword 4
11b
10b
01b
00b
Notes:
1. quadword = 8 bytes
In Figure 54, the processor drives CACHE# throughout all burst
read cycles. In the first burst read cycle, the processor drives
ADS# and CACHE#, then samples BRDY# on every clock edge
starting with the clock edge after the clock edge that negates
ADS#. The processor samples KEN# asserted on the clock edge
on which the first BRDY# is sampled asserted, executes a
32-byte burst read cycle, and expects a total of four BRDY#
signals. An ideal no-wait state access is shown in Figure 54,
whereas most system logic solutions add wait states between
the transfers.
The second burst read cycle illustrates a similar sequence, but
the processor samples NA# asserted on the same clock edge
that the first BRDY# is sampled asserted. NA# assertion
indicates the system logic is requesting the processor to output
the next address early (also known as a pipeline transfer
request). Without waiting for the current cycle to complete, the
processor drives ADS# and related signals for the next burst
cycle. Pipelining can reduce processor cycle-to-cycle idle times.
142
Bus Cycles
Chapter 6