AMD-K6-2E Datasheet, PDF (207/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
Table 32 describes how the PCD signal is driven based on the
values of the CD bit of CR0, the PCD bits, and the PG bit of
CR0.
Table 32. PCD Signal Generation
CD Bit of CR0
1
0
0
0
0
PCD Bit¹
Don’t care
1
0
1
0
Notes:
1. PCD is taken from PTE or PDE.
PG Bit of CR0
Don’t care
1
1
0
0
PCD Signal
High
High
Low
Low
Low
Table 33 describes how the CACHE# signal is driven based on
the cycle type, the CI bit of TR12, the PCD signal, and the
UWCCR model-specific register.
Table 33. CACHE# Signal Generation
Cycle Type
Writebacks
Unlocked Reads
Locked Reads
Single Writes
Any Cycle Except Writebacks
Any Cycle Except Writebacks
Any Cycle Except Writebacks
CI Bit of TR12
Don’t care
0
Don’t care
Don’t care
1
Don’t care
Don’t care
PCD Signal
Don’t care
0
Don’t care
Don’t care
Don’t care
1
Don’t care
Access Within
WC/UC Range¹
Don’t care
0
Don’t care
Don’t care
Don’t care
Don’t care
1
Notes:
1. WC and UC refer to Write-Combining and Uncacheable Memory Ranges as defined in the UWCCR.
CACHE#
Low
Low
High
High
High
High
High
Chapter 8
Cache Organization
189