AMD-K6-2E Datasheet, PDF (133/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
Sampled
NMI is sampled and latched as a rising edge-sensitive signal.
During normal operation, NMI is sampled on every clock edge
but is not recognized until the next instruction boundary. If it is
asserted synchronously, it can be asserted for a minimum of one
clock. If it is asserted asynchronously, it must have been
negated for a minimum of two clocks, followed by an assertion
of a minimum of two clocks.
5.37
PCD (Page Cache Disable)
Pin Attribute
Pin Location
Summary
Output
AG-05
The processor drives PCD to indicate the operating system’s
specification of cacheability for the page being addressed.
System logic can use PCD to control external caching. If PCD is
asserted, the addressed page is not cached. If PCD is negated,
the cacheability of the addressed page depends upon the state
of CACHE# and KEN#.
The state of PCD depends upon the processor’s operating mode
and the state of certain bits in its control registers and TLB as
follows:
s In real mode, or in protected and virtual-8086 modes while
paging is disabled (PG bit in CR0 is 0):
PCD output = CD bit in CR0
s In protected and virtual-8086 modes while caching is
enabled (CD bit in CR0 is 0) and paging is enabled (PG bit in
CR0 is 1):
• For accesses to I/O space, page directory entries, and
other non-paged accesses:
PCD output = PCD bit in CR3
• For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PCD output = PCD bit in page directory entry
• For accesses to 4-Kbyte pages:
PCD output = PCD bit in page table entry
Chapter 5
Signal Descriptions
115