AMD-K6-2E Datasheet, PDF (60/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
Test Register 12
(TR12)
Test register 12 provides a method for disabling the L1 caches.
Figure 32 shows the format of the TR12 register.
63
43 2 1 0
C
I
Reserved
Symbol Description Bit
CI Cache Inhibit Bit 3
Figure 32. Test Register 12 (TR12)
Time Stamp Counter
63
With each processor clock cycle, the processor increments the
64-bit time stamp counter (TSC) MSR. Figure 33 shows the
format of the TSC register.
0
TSC
Figure 33. Time Stamp Counter (TSC)
42
Software Environment
Chapter 3