AMD-K6-2E Datasheet, PDF (203/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
8
Cache Organization
System Bus
Interface Unit
The following sections describe the basic architecture and
resources of the AMD-K6-2E processor internal caches.
The performance of the AMD-K6-2E processor is enhanced by a
writeback level-one (L1) cache. The cache is organized as a
separate 32-Kbyte instruction cache and a 32-Kbyte data cache,
each with two-way set associativity (See Figure 74). The cache
line size is 32 bytes, and lines are prefetched from external
memory using an efficient, pipelined burst transaction.
As the instruction cache is filled, each instruction byte is
analyzed for instruction boundaries using predecode logic.
Predecoding annotates each instruction byte with information
that later enables the decoders to efficiently decode multiple
instructions simultaneously. Translation lookaside buffers
(TLB) are also used to translate linear addresses to physical
addresses. The instruction cache is associated with a 64-entry
TLB, while the data cache is associated with a 128-entry TLB.
32-Kbyte Instruction Cache
Tag
Way 0
State Tag
Way 1
State
RAM
Bit RAM
Bit
64-Entry TLB
Predecode Instruction Cache
Processor
Core
128-Entry TLB
Tag
Way 0
MESI Tag
Way 1
MESI
RAM
Bits RAM
Bits
32-Kbyte Data Cache
Figure 74. Cache Organization
Chapter 8
Cache Organization
185