AMD-K6-2E Datasheet, PDF (188/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
6.6
Special Bus Cycles
The AMD-K6-2E processor drives special bus cycles that
include the following:
s Stop grant
s Flush acknowledge
s Cache writeback invalidation
s Halt
s Cache invalidation
s Shutdown
During all special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1.
BE[7:0]# and A[31:3] are driven to differentiate among the
special cycles, as shown in Table 28. (See also Table 23 on
page 132.)
Note that the system logic must return BRDY# in response to all
processor special cycles.
Table 28. Encodings for Special Bus Cycles
BE[7:0]#
FBh
EFh
F7h
FBh
FDh
FEh
A[4:3]¹
10b
00b
00b
00b
00b
00b
Notes:
1. A[31:5] = 0
Special Bus Cycle
Stop Grant
Flush Acknowledge
Writeback
Halt
Flush
Shutdown
Cause
STPCLK# sampled asserted
FLUSH# sampled asserted
WBINVD instruction
HLT instruction
INVD,WBINVD instruction
Triple fault
Basic Special Bus
Cycle
Figure 69 on page 171 shows a basic special bus cycle.
The processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the
same clock edge that it asserts ADS#.
In this example, BE[7:0]# = FBh and A[31:3] = 0000_0000h,
which indicates that the special cycle is a halt special cycle (See
Table 28). A halt special cycle is generated after the processor
executes the HLT instruction.
170
Bus Cycles
Chapter 6