AMD-K6-2E Datasheet, PDF (208/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
Cache-Related Signals
Complete descriptions of the signals that control cacheability
and cache coherency are given on the following pages:
s CACHE#—page 97
s EADS#—page 101
s FLUSH#—page 104
s HIT#—page 105
s HITM#—page 105
s INV—page 110
s KEN#—page 111
s PCD—page 115
s PWT—page 117
s WB/WT#—page 129
8.4
Cache Disabling and Flushing
To completely disable all cache accesses, the CD bit must be set
to 1 and the cache must be completely flushed. There are three
different methods for flushing the cache. The first method
relies on the system logic, and the other two rely on software.
s For the system logic to flush the cache, the processor must
sample FLUSH# asserted. In this method, the processor
writes back any data cache lines that are in the Modified
state, invalidates all lines in the instruction and data caches,
and then executes a flush acknowledge special cycle (See
Table 23 on page 132).
s The second method relies on software to execute the
WBINVD instruction which causes all modified lines to first
be written back to memory, then marks all cache lines as
invalid. Alternatively, if writing modified lines back to
memory is not necessary, the INVD instruction can be used
to invalidate all cache lines.
s The third method is to make use of the Page Flush/Invalidate
Register (PFIR), which allows cache invalidation and
optional flushing of a specific 4-Kbyte page from the linear
address space (see “Page Flush/Invalidate Register (PFIR)”
on page 200). Unlike the previous two methods of flushing
the cache, this particular method requires the software to be
aware of which specific pages must be flushed and
invalidated.
190
Cache Organization
Chapter 8