AMD-K6-2E Datasheet, PDF (246/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
12.2
Three-State Test Mode
The three-state test mode causes the processor to float its
output and bidirectional pins, which is useful for board-level
manufacturing testing. In this mode, the processor is
electrically isolated from other components on a system board,
allowing automated test equipment (ATE) to test components
that drive the same signals as those the processor floats.
If the FLUSH# signal is sampled Low during the falling
transition of RESET, the processor enters the three-state test
mode. (See “FLUSH# (Cache Flush)” on page 104 for the
specific sampling requirements.) The signals floated in the
three-state test mode are as follows:
s A[31:3]
s ADS#
s ADSC#
s AP
s APCHK#
s BE[7:0]#
s BREQ
s CACHE#
s D/C#
s D[63:0]
s DP[7:0]
s FERR#
s HIT#
s HITM#
s HLDA
s LOCK#
s M/IO#
s PCD
s PCHK#
s PWT
s SCYC
s SMIACT#
s W/R#
The VCC2DET, VCC2H/L#, and TDO signals are the only
outputs not floated in the three-state test mode.
s VCC2DET and VCC2H/L# must remain Low to ensure the
system continues to supply the specified processor core
voltage to the V_CC2 pins.
s TDO is never floated because the boundary-scan Test Access
Port must remain enabled at all times, including during the
three-state test mode.
The three-state test mode is exited when the processor samples
RESET asserted.
228
Test and Debug
Chapter 12